Weird ramblings as I blindly flail my way around learning new tech things
On FPGA memory block optimization
So this is something that bit me in the ass pretty hard recently until someone far more experienced than me on Twitter was able to help me through optimizing my crappy code, and so I figured I’d make a blog post about it. In Verilog, there’s a concept of a memory. A memory is basically…
Day 6: The VCP, VRAM, & Clock Domain Issues
So over the last couple of days I started work on the video co-processor (from here on I think I’ll refer to as the VCP) of the Athena. The goal of this co-processor is to get two independently scrolling tilemap layers, 128 sprites, and 256 onscreen colors. This turned out to be a bit of…
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Stupid Tech Misadventures 